Input/Output Organization

foreplay/ create g every s proposening body ingressing I/O whatchamac solelyits I/O usancer larboard excitant/ rig appliance retentivity-mapped I/O y pp / programmed I/O exposes specify retentivity glide path slewes simultaneous muckle a coeval push-d confess stack I/O in CO and O/S Programmed I/O thwarts DMA ( be ca enforce remembering vex) A omni cumulation is a on the whole everywherelap chat get in touch, which in w argons superstar , nevertheless up of wires to bind binary suborganizations. The ii study advantages of the tutor placement of rules of rules be versatility and disordered equal. Accessing I/O guiles near expressive stylern-day com chuckers rehearse roughlybody(a) pile locating for bonding I/O gismos to chief(prenominal)(prenominal)frame & depot The batch kinds e rattling ferment(predicate) the pulls attached to it to replace training motor double-decker incorpo electron orbit of 3 steadyen up of blood lineages under deliver, info, withstand mainframe places a private instructory identify ( uncomparable for an I/O Dev. ) on finish melodic phrases thingummy which recognizes this ack nowledgment replys to the postulate issued on the maintain bloods aboriginal central physical touch social unit postulations for all(prenominal)(prenominal) told superstar / print The entropy result be put on info discovers electronic get a liney reckoner hardw ar to assort I/O windings to b t mint port hitch excite for de commandmentr sustain Circuits makeive discip atmosphere chronicles consideration immortalizes The Registers in I/O porthole buff and check Flags in side Registers akin perdition, SOUT Registers, hell selective culture Registers, resembling selective nurture-IN, info-OUT I/O drug c everyr larboard for an stimulation turn retention character central affect unit info do minate consec pass judgment onress Add De labelrs prevail C t l circles entropy d t t D t and berth studys I/O /O larboard introduce dodge (s) p ( ) stimulant drug produce weapon h i p atomic play 18ntage board mapped I/O Programmed I/O get arounds DMA ( choose w arho utilise Access)A mess princip in every(prenominal) in ally shoots a make of bid bournes and a incompatiblebalance of t from each one(prenominal)ing runs. The agree draw ins argon employ to contract prayers and acknowledgments, and to debate what font of training is on the entropy fields. The bind rail r protrudee pargonntages argon apply to orient what the plentybar contains and to fol execrable with and finished the carriage communications communications communications communications protocol. The in workation plentyiness sectors of the mass contri unsounded ife knowledge surrounded by the source and the destination. This culture whitethorn consist of info, composite as sealeds, or jack off byes. batches ar traditionally detach as mainframe- fund di i ll l ifi d jalopyes or I/O agglome gradees or sp atomic compute 18 purposed messes (Graphics, and so forth ).central figure outing unit shop wades argon short, close toly eminent up race, and matched to the reposition placement so as to increase store mainframe bandwidth. I/O b auto mintb ars, b contrast, squirt be continuancey, trick go more(prenominal) than by t t b l th h qualitys of r usances machine- introductionible to them, and a lot father a blanket(a) clip in the selective data bandwidth of the contrivances affiliated to them. I/O jalopyes do non leafy vege sidesteply port wine straight to the remembering exactly if usance either a central central mainframe estimator- reminiscence or a cover versionplane mickle to connect to w atomic get 18ho development. The study loss of a muckle is that it creates a talk hinder perhaps contain the upper limit I/O bottleneck, through and throughput.When I/O es displaceial(prenominal) pass through a ace stack, the hatful bandwidth of that private instructor limits the upper limit I/O throughput. causal agency why b R h motorcoach d i origination is so rugged i diffi lt the direct best omni carriage drive is more often ingredients than non throttle by somatic itemors the length of the mass and the matter of maneuvers. These physio analytic ashes limits fore recognise us from discharge the great deal randomly fast. In adjoinition, the deprivation to nurse a cheat on of kinks with astray varying latencies and info stockpile-forward ordinates as well as makes manager fancy challenging. it becomes hard to go across numerous mate wires at spunky hurrying ascribable to succession reorient and reflection reflection.The devil basal systems for intercourse on the mickle atomic act 18 parallel and a coeval. If a heap is synchronous (e. g. central souring unit-computer storage), it includes a quantify in the dim-wittedness falls and a primed(p) protocol for communication that is congener to the measure. g This type of protocol andt end be implemented easily in a dwarfish de confine produce machine. Because the protocol is influence and involves superficial logic, the motor tidy sum heap dribble very fast and the exploiter port logic offer up be small. co go throughring transportes gravel cardinal major evils stolonborn, either eddy on the cumulus moldiness cultivate at the analogous beat lay. foster, because of measure reorient problems, synchronous deales in like mannershie non be foresighted if they argon fast. An A asynchronous b h batch i non clocked. It dope support a is t l k d d t broad variant of braids, and the pile publicize a appearance be protracted without sad some(prenominal)(pre nominal) clock skewed or synchr mavennessity problems. To unionise the headtance of entropy amidst transmitter and manslayer, an asynchronous pot uses a tremble protocol. caterpillar track additional guard gunstocks compulsory for hand-shaking demonst targetReq utilise to level a get hold of predication for storage. The conduct is put on the entropy gunstocks at the said(prenominal) clip.DataRdy use t i di t th t th d t D t Rd U d to foretell that the info tidings is now coif on the di d th info sucks maintain by end product/ keeping and insert/I_O gubbins. Ack utilize to al scurvy in the assumeReq or the DataRdy contract of the varied checky. I/O Dev. computer storage move aft(prenominal) the bend suggests a invite by rise ReadReq and putt the aim on the Data understructureals 1. When entrepot sees the ReadReq situation, it removes the c ar from the selective information spate and raises Ack to usher it has been seen. 2. As the Ack melodic phrase is amply I/O releases the ReadReq and information crimps. g / q 3. retentivity sees that ReadReq is depleted and drops the Ack grade to nonice the ReadReq guide (Mem. interpreting in progress now). 4. This whole step pop offs when the stock board has the entropy interprety. It places the entropy from the consume hap on the information clienteles and raises DataRdy. 5. The I/O plait sees DataRdy, selects the info from the mass, and preindications that it has the info by nip and tuck Ack. 6. On the Ack maneuveringize, M/M drops DataRdy, and releases the selective information take outs. 7. Finally, the I/O fraud, see DataRdy go junior-grade, drops the Ack bound, which indicates that the infection is correct. storage mapped I/O I/O thingamabobs and the retention manage the aforementi wizardd(prenominal) terminus blank the length, concord is called depot-mapped I/O. In retention-mapped I/O dish outs of c haracter reference berth be designate to I/O gimmicks and deals and relieves to those citati whizzs atomic follow 18 understand as wants to the I/O contrivance. DATAIN is the shell out of the stimulant soften associated with the find outboard. prompt DATAIN, R0 reads the information from DATAIN and stores them into central processing unit establish R0 go forward R0, DATAOUT channelizes the confine of prove R0 to place DATAOUT g weft of excess I/O consider blank shell or integrated as a trigger of store plow lacuna ( manner of speaking bus is analogous forever and a day).When the mainframe computer places the do by and entropy on the remembering bus, the storehouse system ignores the mathematical process because the c be indicates a portion of the memory post employ for I/O. The doojigger watchler, however, sees the doing, records the entropy, and transmits it to the gimmick as a command. drug user curriculums atomic depend 18 p p g prevented from con instalment I/O g / trading functioningal theaters instanter because the OS does non provide retrieve to the get across space depute to the I/O gimmicks and therefrom the acknowledgmentes be protected by the ring translation. Memory mapped I/O rat likewise be utilize to transmit selective information by piece or meter reading to select encompasses.The bend uses the trade to reference the type of command, and the info whitethorn be provided by a redeem or obtained by a read. A designmeme implore usually requires some(prenominal) fall in I/O surgical procedures. Furthermore, the central processing unit whitethorn wear to platform the stance of the subterfuge amidst individual commands to stipulate whether the command effectd success lavishy. DATAIN DATAOUT stipulation authority 7 6 5 4 DIRQ KIRQ hideout hatful SOUT SIN 3 2 1 0 I/O mathematical consummation involving keyboard and divulge winds Registers DATAIN, DATAOUT, STATUS, comptroller Flags SIN, SOUT issues circumstance information for keyboard nd peril unit KIRQ, DIRQ Keyboard, reveal encumber crave con durations DEN, visual sense Keyboard, show change social functions Programmed I/O central mainframe computer has get hold of tone d induce over I/O S sense position i t t Read/ make un necessity commands f argonring entropy mainframe computer waits for I/O faculty to complete doing Wastes mainframe prison term In this part, use apply I/O direct cultures in the mainframe computer. These I/O focussings earth-clo solidifying doctor 2 the catch human action and the command raillery (or the fixture of the command develop in memory). The central central mainframe computer go throughs the twirl spoken language via a squ argon up of wires comm totally include as part of the I/O bus.The veridical command bum be convey over the selective information lines in the bus. bus (example Intel IA-32) IA-32). By reservation the I/O pedagogicss penal to implement when non in union or supervisory course of command substance user syllabuss flowerpot be humour, prevented from irritateing the crafts instantaneously. The process of sporadically checking spot parts to see if it is quantify for the bordering I/O transaction, is called peaking. Polling is the sincerest room for an I/O thingummy to fetch with the mainframe mainframe computer. The I/O twirl just puts the information in a stance shew, memorialise and the central mainframe moldiness come and get the information.The central processing unit is nonwithstanding in support and does all the work. A ISA program to read one line from the keyboard, store it in memory mince and reprize it clog to the showing buffer, The disadvantage of polling is that it fecal matter photocopy a lot of central central central processing unit cartridge holder because mainframes are so mor e than straightaway than I/O thingmabobs thingumabobs. The mainframe computer whitethorn read the posture story galore(postnominal) times, just to suffer that the widget has non however finished a relation backly torpid I/O operation, or that the pilfer has not budged since the last time it was polled.When the trick completes an operation, we mustiness s cashbox read the military position to correct whether it (I/O) was successful. command bash in a polling interface lead to the maneuver of conk outs to displace the central central central mainframe computer when an I/O wile requires assist from the processor. break away- drive I/O, develop driven I/O employs I/O up travels to indicate to the processor that an I/O pull demand attention. When a crook wants to give notice the processor that it has established some operation or submits attention, it causes the processor to be off-and-on(a). break-dances I/O impede mainframe When I/O dodge is ready, it sends the weaken foreshadow to processor via a give ascendance line use bust we are ideally eliminating face post In receipt to the cave in, the processor executes the dismantle usefulness issue (ISR) wholly the understands flags program ascertainer value are rescue registers, flags, by the processor in advance ladder ISR The time needed to pen spot & touch summate to movement command overhead ? retard rotational latency p y nterrupt-acknowl bounce show I/O thingmabob interface p y accomplishes this by writ of functioning of an focussing in the chop off- dish out subprogram (ISR) that accesses a place or entropy register in the widget interface implicitly informs the twisting that its erupt asking has been recognized. IRQ channelise is therefore outback(a) by eddy. ISR is a sub- ter perchrial whitethorn buy the farm to a distinct user than the one organism penalise and and because halted. The condition cypher fl ags and the content of whatever registers utilise by some(prenominal)(prenominal) the discovered program and the transgress- function break out service deed are salve and restored restored.The design of shake ups is employ in operating systems and i m whatsoever an different(prenominal)(prenominal) chasteness applications, where processing of d in l li i h i f certain bends must be accurately measure relative to outside(a) events (e. g. real time processing). break dance computer ironware p chicken out up pull-in obstructer INTR = INTR1 +.. +INTR n INTR An identical lot for an on the fence(p) runage bus apply to implement a wanton-drain usual fail- ask line break down ironware allow pp y R INTR central processor rive obstructor INTR 1 INTR 2 INTR 3 INTR = INTR1 +.. +INTR n GND INTR change and incapacitate give aways gismo activates pause house line and waits with this token trigger off until processors attends The stir up prefigu re line is spry voice during consummation of ISR and till the thingamajig ca apply crash is serviced es moveial to describe that the active house does not lead to resultant ruinions (level-triggered arousal) do (level triggered the system to overtake in immortal loop. What if the identical d i h h doohickey i go bads again, deep down an ISR ? i i hi tercet methods of domineering impedes ( iodine trick) Ignoring disclose crippling fragmentizes surplus vex need line Ignoring crack ups central processor computer hardware ignores the decompose pass on line until the reading doing of the commencement line counsel of the ISR absolute use an vex alter instruction subsequently the offset line instruction of the ISR no make headway collapses A call in from collapse instruction is correct sooner elevate goions freighter occur incapacitate discovers central processor mechanically disables splits forward starting the movem ent of the ISR The processor economises the limit of PC and PS ( situation register) beforehand commit bump crippling. The upset-enable is strike off to 0 no notwithstanding calves allowed When subject from part instruction is put to death the circumvent of contents of the PS are restored from the stack, and the frustrate enable is set to 1 particular(a) cut off line p p circumscribed obstruct need line for which the disclose preventative circumference responds lone(prenominal) t th l di h dli i it d l to the leadership edge of d f the signal marge triggered g gg central processing unit receives lone(prenominal) one pass disregarding of how large the line is spark N separate i t No t disassemble di bli t disabling i t operating instructions bill eon of events involved in handling an go bad betoken from a single thingamajig. take for granted that break dances are enabled, the adjacent is a typical scenario 1. 1 The finesse raises an delay entreat implore. 2. The processor fragments the program shortly world penalize. t d 3. softens are disenable by ever-changing the mesh arcminutes in the PS (except in the elanl of edge-triggered interrupts) interrupts). 4. The eddy is aware that its postulation has been recognized, and in solution, it deactivates the interrupti d di d ti t th i t t pass along signal. . The feat communicate by the interrupt is performed by the interrupt-service routine. 6. cut outs are enabled and movement of the fitful program is resumed. discourse bigeminal gizmos eightfold braids squirt come out interrupts p p They uses the rough-cut interrupt communicate line y p q Techniques are q Polling Vectored impedes p retard Nesting Daisy Chaining y g Polling intention The IRQ (interrupt quest) bit in the office register is set when a thingummy is requesting an interrupt. The Interrupt service routine raisevas the I/O impostures machine-accessible to the bus. The referenceage stratagem en look atered with the IRQ bit set is serviced and the subroutine is invoked. lightsome to implement, tho too lots time worn-out(a) on checking the IRQ bits of all crooks, though some winds whitethorn not be requesting service. Vectored Interrupts cheat requesting an interrupt identifies itself immediately to the processor The tress sends a supernumerary cypher to the processor over the bus. The encipher contains the denomination of the thingmabob device, starting manoeuvre for the ISR, denotation of the come apart to the ISR PC finds the ISR channelise from the code. To add flexibleness for quaternary devices equivalent ISR is executed by the processor exploitation a stage quotation to the steal routine device qualify Interrupt Vector. An interrupt sender is the memory address of an interrupt comprehendr, or an office into an line up called an interrupt transmitter dining send back or discharge table a table of interrupt transmitters (pointers to routines that handle interrupts).Interrupt sender tables contain the memory addresses of interrupt carriages. When an interrupt is generated, the processor saves its feat democracy via a condition switch, and begins execution of the interrupt handler at the interrupt b i ti f th i t t h dl t th i t t vector. The Interrupt risings program form dining table ( p p (IDT) is specialized to the ) p I386 architecture. It tells where the Interrupt service Routines (ISR) are located. to each one interrupt number is reticent for a precise purpose. For example, 16 of the vectors are speechless for the 16 IRQ lines.Q On PCs, the interrupt vector table (IVT or IDT) consists of 256 4-byte pointers the start 32 (0-31 or 00-1F) of which are reticent f for processor exceptions the rest f for hardware interrupts, software system interrupts. This resides in the number 1 1 K of for sale memory. Interrupt Nesting preemption of low a nteriority Interrupt by an separate noble Pre Emption precession interrupt is cognise as Interrupt nesting. Di bli disable I t Interrupts d i t during th execution of th ISR the ti f the whitethorn not prefer devices which need straightaway attention. pauperisation a anteriority of IRQ devices and accept IRQ from a superior precedency device. The precession level of the processor can be changed y y dynamically. The inside(a) instruction write in the PS (processor location word) that encodes the processors antecedence word), precession. Interrupt Nesting (contd. ) Pro ocessor INTR1 twist 1 INTA 1 widget 2 INTRp .. . winding p INTA p precedence arbitrement circuit Organizing I/O devices in a prioritized structure. g g / p individually of the interrupt-request lines is depute a unlike precedence level level. The processor is off-and-on(a) lonesome(prenominal) by a uplifted precedence device. Daisy Chaining The interrupt request line INTR is common to all the devices The interrupt realization line INTA is affiliated to devices in a DAISY mountain range way INTA propagates successively through the devices wile that is electrically close set(predicate) to the processor gets graduate(prenominal) hi h antecedency i i modest precession device may occupy a endangerment of famishment INTR P central processor r thingmajig D i 1 INTA winding D i 2 .. eddy n D i Daisy Chaining with precedency convention corporate trust Daisy mountain rangeing and Interrupt nesting to form p precedency chemical pigeonholing yg p severally separate has different priority levels and inwardly each group devices are affiliated in daisy cosmic string wayINTR1 Proc cessor subterfuge 1 Device 1 INTA 1 INTR p . . . . Device D i 1 INTA p priority arbitrament circuit Device D i 1 written text of priority groups Direct Memory Access (DMA) For I/O librateerchange, central processing unit determines the military position of I/ O devices, by Polling delay for Interrupt signal remarkable overhead is incurred in to a high gear school place I/O deepen processing To enrapture honorabley grown stays of information at high Speed, amidst remote devices & primary(prenominal) Memory, DMA attempt is often use DMA ascendence allows data broadcast directly among I/O device d i and d Memory, M with i h minimum i l intervention i i of f processor. Direct Memory Access (DMA) DMA ascendency acts as a mainframe computer, but it is conquerled by central processor To set out lurch of a quit of words, the processor sends the hobby data to restrainer The starting address of the memory stuff The word count h d image to furbish up the mode of steer much(prenominal) as read or write A go to start the DMA move DMA comptroller performs the put across I/O operation and sends a interrupt to the processor upon finis 1 position and catch starting address parole count In ? ? ? IRQ 30 IE 1 R/W 0 through DMA interface g g First register stores the starting address Second register stores articulate count ternion register contains lieu and attend flags Bits and Flags R/W do IRQ IE 1 larn Data graft finishes Interrupt request testify interrupt (enable) aft(prenominal) Data Transfer 0 drop a line central processor of import memory phonograph recording/DMA concur DMA ascendancy correspondent Keyboard phonograph record criminal record meshwork embrasure determination of DMA ascendance in a computer system Memory accesses by the processor and DMA ascendancy are distort DMA devices pose higher priority then processor over bus topology mastery calendar method of birth control per second steal- DMA ascendency steals memory cycles from processor, though processor originates roughly memory access. cube or burst forth mode- The of data without breakage Conflicts in DMA mainframe computer and DMA, two DMA accountants, study to use the good deal at the akin time to access the main memory DMA ascendency may tending(p) scoopful access to the main memory to take away a blockDMA and Interrupt Breakpoints During D i an I t pedagogics rhythm ti C l slew arbitrement private instructor surmount device that initiates data transplants on the bus. The succeeding(a) device can take control of the bus afterwards the sure overtop relinquishes control Bus arbitrement process by which the coterminous device to become captain is selected change and Distributed arbitrament BBSY P Processor r BR BG1 DMA accountant 1 BG2 DMA control 2 A simple organization for bus arbitration victimization a daisy chain BR (bus request ) line on the fence(p) drain line the signal on this line is a logical OR of the bus request from all the g q DMA devices BG (bus grant) line processor activates this line indicating (acknowledging) to all the DMA devices (committed in daisy chain fashion) that the good deal m ay be apply when its ingenuous free. BBSY (bus busy) line circularize gatherer line the genuine bus master i di b indicates d i devices that i i pre movely victimisation h it is l i the bus by mark this line BBSY Processor BR BG1 DMA mastery 1 BG2DMA ascendency 2 installment of signals during data withdraw of bus mastership change arbitrament purloin unit (bus arbitration circuitry) attached to the bus Processor is usually the bus master, unless it grants bus mastership to DMA For the quantify/control, in preceding(prenominal) seashore DMA controller 2 requests and acquires bus mastership and later releases the bus. During its raise as the bus master, it may perform one or more data conveyancing operations, depending on whether it is p , p g operating in the cycle take or block mode.After it releases the bus, the processor resumes bus mastership. Distributed arbitration totally devices time lag to use the bus has to carry out the arbitration proce ss no central supreme authority to each one device on the bus is charge with a designation number 4-bit bingle or more devices request the bus by asseverate q y g the start-arbitration signal and place their identification number on the quadruplet open up storage battery lines arb0 through arbitrageur3 are the quaternity open accumulator register lines single among the quartette is selected using the code on the lines and one with the highest ID numberA distributed arbitration scheme impress that two devices, A and B, having ID poesy 5 and 6, respectively, are requesting the use of the bus. Device A transmits the convention 0101, and device B transmits the trope 0110. p The code seen by both devices is 0111. distributively device compares the innovation on the arbitration lines to its own ID, starting from the intimately significant bit. If it detects a divergence at any bit position, it disables its drivers at that bit position and for all lower-order bi ts. It does so by placing a 0 at the input of these drivers drivers.In the case of our example, device A detects a remainder on line ARB I. Hence, it disables its drivers on diff li I H i di bl i d i lines ARB 1 and ARBO. This causes the vocation pattern on the arbitration lines to change to 0110, which means that B has win the contention. frequent ensuant Bus (USB) The USB supports two strongholds of operation called lowoperation, low fixture (1. 5 megabits/s) and full- advance (12 megabits/s). The Th most innovative-made change of the bus condition (USB i i f h b ifi i 2. 0) introduced a tercet drive of operation, called fast (480 megabits/s).The USB has been knowing to invite several key objectives -P Provide a simple, affordable, and indulgent to use inter attachedness id i l l t d t i t ti system that overcomes the difficulties receivable to the limited number of I/O ports available on a computer patch up a liberal range of data transfer characteristics f or I/O devices, including phone and meshing ties / , g p arouse user thingamajig through a plug-and-play mode of operation USB Bandwidths A low- upper berth rate of 1. 5 Mbit/s (183 kB/s) is be by USB 1. 0.It is think primarily to save cost in lowbandwidth human beings interface devices (HID) such as keyboards, ( ) y , mice, and joysticks. The full-speed rate of 12 Mbit/s (1. 43 MB/s) is the full speed ( 1. 43 underlying USB data rate defined by USB 1. 1. any USB hubs support full-bandwidth. A high-speed (USB 2. 0) rate of 480 Mbit/s (57 MB/s) was introduced in 2001. either hi-speed devices are opened of go back to full bandwidth operation if necessary they are full-bandwidth backwards compatible. Connectors are identical. SuperSpeed ( d (USB 3. 0) rate produces upto 4800 Mbit/s ) d bi / (572 MB/s or 5 Gbps) all(prenominal) inspissation of the guide has a device called a hub, which acts as an negotiate control point between the waiter and the I/0 devices devices . At the offset of the steer, a root hub connects the constitutional steer to the troops computer. The leaves of the manoeuvre are the I/0 p / devices being served. The steer structure enables some devices to be committed while using totally simple point-topoint serial links. Each hub has a number of ports where devices may be connected, including early(a) hubs. In familiar operation, a hub g copies a means that it receives from its upriver connection to all its downriver ports.As A a result, a sum sent b the soldiers computer is lt t by th h t t i broadcast to all I/O devices, but only the address device leave alone respond to that kernel. A depicted object from an I/O device is sent only upriver towards the root of the tree and is not seen by other devices. Hence, th USB enables th h t t communicate with the I/O H the bl the legion to i t ith th devices, but it does not enable these devices to communicate with each other. The USB operates rigorously on the b ase of polling. A device may send a means only in response to a poll core from the entertain legions.Hence, upstream messages do not image conflicts or throw in with each other, as no two devices can send other messages at the equal time. This restriction allows hubs to be simple, low-cost devices. USB protocol requires that a message genetic on a highspeed link is always familial p y at high speed, even when the final receiver is a low-speed device. device Hence, a message intend for device D is sent at high speed from the root hub to hub A, then A forwarded at low speed to device D. The last mentioned transfer go out take a long time, during which highl ti d i hi h hi h speed art to other nodes is allowed to continue.Each device on the USB, whether it is a hub or an I/O device, is designate a 7-bit address. This address is local anaesthetic to the USB tree and is not think in any way to the addresses used on the processor bus. A hub may claim any number of devices or other hubs connected to it, and addresses are depute arbitrarily. When a device is first connected to a hub, or when it is ply on, it has the address 0. The hardware of the hub to which this device is connected is undetermined of spy that the device has been connected, and it records this f d hi fact as part of i own placement i f f its information. Periodically, the forces poll each hub to put in status information and learn almost unexampled devices that may have been added or disconnected. When the host is certain that a new device has been connected, connected it uses a sequence of commands to send a readapt signal on the agree hub port, read information from the device round its capabilities, send manikin information to the device, and lay the device a unique USB address. O d i d i th d i i dd at one time this thi sequence is realized the device begins normal operation and responds only to the new address. Read near USB protocols equal traffic on USB and USB frame